ATA8743-PXQW【PDF 178/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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178

9152BINDCO02/10

ATA8743

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V

reset protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low V

. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

27.1.4

Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 27-1 shows the typical pro-

gramming time for Flash accesses from the CPU.

Note:

1. The min and max programming times is per individual operation.

27.2 Register Description

27.2.1

SPMCSR Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

" Bits 7..5 Res: Reserved Bits

These bits are reserved bits in the ATtiny24/44/84 and always read as zero.

" Bit 4 CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

" Bit 3 RFLB: Read Fuse and Lock Bits

An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,

will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-

tion register. See EEPROM Write Prevents Writing to SPMCSR on page 177 for details.

" Bit 2 PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

Table 27-1. SPM Programming Time

(1)

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

Bit

0x37 (0x57)

CTPB

RFLB

PGWRT

PGERS

SPMEN

SPMCSR

Read/Write

R/W

Initial Value

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